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✏️ /usr/include/drm/drm_sarea.h

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/**
 * \file drm_sarea.h
 * \brief SAREA definitions
 *
 * \author Michel Dänzer <michel@daenzer.net>
 */

/*
 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef _DRM_SAREA_H_
#define _DRM_SAREA_H_

#include "drm.h"

#if defined(__cplusplus)
extern "C" {
#endif

/* SAREA area needs to be at least a page */
#if defined(__alpha__)
#define SAREA_MAX                       0x2000U
#elif defined(__mips__)
#define SAREA_MAX                       0x4000U
#elif defined(__ia64__)
#define SAREA_MAX                       0x10000U	/* 64kB */
#else
/* Intel 830M driver needs at least 8k SAREA */
#define SAREA_MAX                       0x2000U
#endif

/** Maximum number of drawables in the SAREA */
#define SAREA_MAX_DRAWABLES		256

#define SAREA_DRAWABLE_CLAIMED_ENTRY    0x80000000

/** SAREA drawable */
struct drm_sarea_drawable {
	unsigned int stamp;
	unsigned int flags;
};

/** SAREA frame */
struct drm_sarea_frame {
	unsigned int x;
	unsigned int y;
	unsigned int width;
	unsigned int height;
	unsigned int fullscreen;
};

/** SAREA */
struct drm_sarea {
    /** first thing is always the DRM locking structure */
	struct drm_hw_lock lock;
    /** \todo Use readers/writer lock for drm_sarea::drawable_lock */
	struct drm_hw_lock drawable_lock;
	struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES];	/**< drawables */
	struct drm_sarea_frame frame;	/**< frame */
	drm_context_t dummy_context;
};

typedef struct drm_sarea_drawable drm_sarea_drawable_t;
typedef struct drm_sarea_frame drm_sarea_frame_t;
typedef struct drm_sarea drm_sarea_t;

#if defined(__cplusplus)
}
#endif

#endif				/* _DRM_SAREA_H_ */

Batal

⬅ include 32 item

Nama	Tipe	Ukuran	Diubah	Perm	Aksi
📄 amdgpu_drm.h	h	50.9 KB	10/07/26 05:59	0644	✏️ ⬇
📄 amdxdna_accel.h	h	16.7 KB	10/07/26 05:59	0644	✏️ ⬇
📄 armada_drm.h	h	1.2 KB	10/07/26 05:59	0644	✏️ ⬇
📄 asahi_drm.h	h	35 KB	10/07/26 05:59	0644	✏️ ⬇
📄 drm.h	h	46.5 KB	10/07/26 05:59	0644	✏️ ⬇
📄 drm_fourcc.h	h	75.7 KB	10/07/26 05:59	0644	✏️ ⬇
📄 drm_mode.h	h	40.8 KB	10/07/26 05:59	0644	✏️ ⬇
📄 drm_sarea.h	h	2.7 KB	10/07/26 05:59	0644	✏️ ⬇
📄 etnaviv_drm.h	h	11.7 KB	10/07/26 05:59	0644	✏️ ⬇
📄 exynos_drm.h	h	10.9 KB	10/07/26 05:59	0644	✏️ ⬇
📄 habanalabs_accel.h	h	79.6 KB	10/07/26 05:59	0644	✏️ ⬇
📄 i915_drm.h	h	128.6 KB	10/07/26 05:59	0644	✏️ ⬇
📄 ivpu_accel.h	h	14.4 KB	10/07/26 05:59	0644	✏️ ⬇
📄 lima_drm.h	h	4.9 KB	10/07/26 05:59	0644	✏️ ⬇
📄 msm_drm.h	h	20.7 KB	10/07/26 05:59	0644	✏️ ⬇
📄 nouveau_drm.h	h	14.7 KB	10/07/26 05:59	0644	✏️ ⬇
📄 nova_drm.h	h	2 KB	10/07/26 05:59	0644	✏️ ⬇
📄 omap_drm.h	h	3.9 KB	10/07/26 05:59	0644	✏️ ⬇
📄 panfrost_drm.h	h	8.9 KB	10/07/26 05:59	0644	✏️ ⬇
📄 panthor_drm.h	h	31.1 KB	10/07/26 05:59	0644	✏️ ⬇
📄 pvr_drm.h	h	39.2 KB	10/07/26 05:59	0644	✏️ ⬇
📄 qaic_accel.h	h	11.8 KB	10/07/26 05:59	0644	✏️ ⬇
📄 qxl_drm.h	h	4 KB	10/07/26 05:59	0644	✏️ ⬇
📄 radeon_drm.h	h	37.3 KB	10/07/26 05:59	0644	✏️ ⬇
📄 rocket_accel.h	h	3.8 KB	10/07/26 05:59	0644	✏️ ⬇
📄 tegra_drm.h	h	21.1 KB	10/07/26 05:59	0644	✏️ ⬇
📄 v3d_drm.h	h	23.8 KB	10/07/26 05:59	0644	✏️ ⬇
📄 vc4_drm.h	h	14.1 KB	10/07/26 05:59	0644	✏️ ⬇
📄 vgem_drm.h	h	1.9 KB	10/07/26 05:59	0644	✏️ ⬇
📄 virtgpu_drm.h	h	7.9 KB	10/07/26 05:59	0644	✏️ ⬇
📄 vmwgfx_drm.h	h	36.7 KB	10/07/26 05:59	0644	✏️ ⬇
📄 xe_drm.h	h	77.4 KB	10/07/26 05:59	0644	✏️ ⬇

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